The advent of wireless communication leads to increasing demands on wireless communication devices to comply with increasingly complicated communication specifications. A wireless communication device transmits and receives modulated radio frequency (RF) signals, generally in accordance with one or more telecommunication standards. Wireless communication devices typically include a frequency synthesizer to generate the desired modulation frequency for the radio frequency (RF) transmitter and RF receiver. In order to cover multiple frequency bands and to meet the demand of fine frequency step size, fractional-N frequency synthesizers are often employed. Furthermore, wireless communication standards often bind large number of channels into a narrow frequency band. The frequency synthesizer for these wireless applications must be capable of covering the wide frequency range while ensuring low jitter on the output frequency signal.
Phase-locked loops (PLL) are widely used as the basis for frequency synthesizer circuits. A phase-locked loop (PLL) is an electrical circuit that controls an oscillator so that the oscillator maintains a constant phase angle relative to a reference signal. In general, a PLL is formed by a phase detector, a charge pump, a low pass filter, and a voltage-controlled oscillator (VCO). The PLL receives an input signal and operates to control the VCO to lock to the frequency indicated by the input signal so that the output oscillating signal of the VCO maintains a fixed phase relationship with the input signal.
FIG. 1 is a schematic diagram of a conventional phase-locked loop (PLL) circuit. Referring to FIG. 1, a phase-locked loop (PLL) circuit 10 receives an input signal 12 generated by an oscillator 11 having an input frequency fin and generates an output signal 22 having an output frequency fout where the output signal 22 has a fixed relation to the phase of the input signal 12. The PLL circuit 10 may include a frequency divider 13 to divide down the input frequency, such as by a division factor of M, to generate a reference signal 15 having a reference frequency fref. The PLL circuit 10 includes a phase and frequency detector (PFD) 14, a charge pump 16, a low pass filter 18 and a voltage controlled oscillator (VCO) 20. The low pass filter 18, also referred to as a loop filter, is typically implemented as a serial connection of a capacitor and a resistor. PLL circuit 10 also includes a feedback frequency divider 30 forming a negative feedback loop. The feedback frequency divider 30 receives the output signal 22 and generates a feedback signal 34 having a divided-down feedback frequency ffb, such as by a division factor of N. The feedback signal 26 is coupled to the phase and frequency detector 14 to form the feedback loop.
The operation of PLL 10 is well known. The phase and frequency detector 14 compares the phase difference between the reference signal 15 and the feedback signal 34. The phase difference is used to control the charge pump 16 which generates a control signal for controlling the VCO 20. The control signal is coupled to the low-pass filter 18 to filter out high frequency changes to generate the control voltage Vctrl for driving the VCO 20. The VCO 20 generates the output signal 22 having a fixed relation to the phase of the input signal. The output signal 22 is fed back to the phase and frequency detector 14 through the feedback frequency divider 30. The output frequency thus generated is a function of the input frequency and the division factors N and M and given as: fout=N/M fin.
The VCO of a PLL generates the output frequency based on the control voltage Vctrl applied to a VCO operating curve. In order to generate an output frequency with a wide frequency range, a single-curve VCO may be used but the VCO will need to have a large VCO gain, represented by a steep slope in the single VCO operating curve, as shown in FIG. 2(a). A large VCO gain is often undesirable as small changes in the control voltage Vctrl will lead to large change in the output frequency and resulting in undesirable jitters. In some examples, the jittering problem is controlled by limiting the variation in the control voltage. In other cases, a multi-curve VCO with multiple VCO operating curves, as shown in FIG. 2(b), is used. When a multi-curve VCO is used, each VCO operating curve has a smaller VCO gain, represented by a shallower slope for each curve, while the set of operating curves covers the desired wide frequency range.
FIG. 3 is a schematic diagram of a conventional fractional-N frequency synthesizer incorporating a multi-curve VCO. Referring to FIG. 3, a fractional-N frequency synthesizer 50 is formed using a basic phase-locked loop (PLL) structure including a phase and frequency detector (PFD) 54, a charge pump 56, a low pass filter 58 and a voltage controlled oscillator (VCO) 60. An oscillator 52 may be used to generate the reference frequency fref, as the input signal to the phase and frequency detector 54. A feedback frequency divider 64 is used in the feedback path. The feedback frequency divider 64 is implemented as a multi-modulus divider with a division ratio N, also referred to as the modulus of the divider 64. Accordingly, the output frequency fout is N times the reference frequency fref, given as: fout=N*fref. In a fractional frequency synthesizer, the output frequency fout is a fraction of the input reference frequency fref and the divider ratio N includes an integer part and a fractional part. As a multi-modulus divider, the feedback divider 30 is implemented as a chain of divider cells and has a given division range.
In operation, the reference frequency fref is generated from the oscillator 52. The reference frequency fref is typically a high frequency signal and is divided down by the feedback frequency divider 64 to a desired lower frequency as the output frequency fout. The output frequency fout is locked to the reference frequency fref through the PLL. The feedback frequency divider 64 receives the output frequency fout as the input source frequency and generates a divided down frequency as the feedback frequency ffb to the PLL. The output frequency fout is adjusted by changing the division ratio N of the feedback frequency divider 64. Fine frequency step size can be achieved by constantly swapping the feedback division ratio N between integer numbers, such as from N, to N−1, N+1, N−2, N+2, etc.
The division ratio N of the feedback frequency divider 64 is modulated by a modulator 68. The modulator 68 generates control databits to control the division factor of the divider cells in the divider 64 to realize the desired division ratio N. The modulator 68 receives the feedback frequency fb and the control databits are generated synchronous to the feedback frequency ffb. In practice, the modulator 68 randomizes the choice of the modulus between integers D and D+1 to generate the fractional division ratio N.
When a frequency synthesizer uses a multi-curve VCO, a control circuit is used to select a desired VCO operating curve for a given target output frequency. The operation to select a VCO operating curve is often referred to as “coarse control.” After the desired operating curve is selected, the PLL of the frequency synthesizer operates using “fine control” to adjust the control voltage Vctrl driving the VCO to vary the output frequency along the selected VCO operating curve. Conventional methods for coarse control, or searching and selecting an operating curve, in a multi-curve VCO often employ open loop control and often do not select the optimal operating curve. In some cases, the conventional search methods may cause the VCO to be stuck at a sub-optimal operating curve which impedes the operation of the frequency synthesizer.